A cell-based integrated circuit is formed by selecting a plurality of cells that represent components having different characteristics from one or more cell libraries, determining interconnects for the selected cells, and then placing and routing the interconnected selected cells to form the integrated circuit. For example, groups of cells may be interconnected to function as flip-flops, shift registers and the like. This process, overall, is conventionally described in terms of logic description, synthesis of that logic, and then placement and routing of the synthesized logic.
Electrical connections of individual components on integrated circuits are achieved using conducting paths (also called "wires" or "nets") between terminals of components which are to be connected. Automatic routing schemes are used to determine these conducting paths.
For more complex designs, there are typically at least four distinct layers of conducting medium available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing. It is a common practice to route each conducting path ("wire" or "net") by using one or more of the distinct layers of conducting medium, with one layer of a pair being reserved predominantly for connections running along the "x" direction and the other layer for connections running in the orthogonal or "y" direction. Some of the layers, such as the metal layers, are exclusively used for interconnection of components. The polysilicon layer may have a dual role, such as forming the gates of transistors as well as for interconnection of components.
An electrical connection between two nets on adjacent layers is implemented with a "via" which is an etched or drilled hole in the substrate for allowing a conductive path to extend from one layer to another layer.
Conventional design methodologies typically use a two-step process for determining the final size and location of each net. The first step is the global routing step for roughly determining wiring routes. The "rough" wiring pattern generated in this step is known as a "global route." Subsequently, a second detailed routing step for precisely determining a final routing pattern according to the global routes is used. This final routing pattern determined by the detailed routing step is known as a "detailed route."
In one conventional design methodology, die size is fixed and imaginary grid lines are used to partition the die into a matrix of blocks. Thus, the grid lines are used by the automated place and route equipment to assist in determining and then tracking of the location of the various nets and components that make up the integrated circuit.
With conventional "fixed die" design methodologies, complete routing of all nets cannot be ensured. Although complete routing can be ensured using channel routing techniques, channel routing techniques impose additional constraints and have their own problems.
Co-pending related U.S. Patent Application entitled "Timing Closure Methodology," which is fully incorporated herein by reference, describes a timing driven methodology, which methodology makes timing, but not area, a constraint. Accordingly, once placement of cells is determined based upon timing that has been fixed, the need exists to more efficiently route wires. Conventional routing techniques, including those mentioned above, can be used to route wires and connect cells whose placement has been determined by use of the timing driven methodology described above. However, conventional routing methodologies cannot efficiently ensure that the timing constraints are maintained. Accordingly, there is a need for a new routing method that works with the timing driven design methodology to provide more efficient and better results.